1. Field of the Invention
The present invention relates to a memory apparatus and an operation method thereof. More particularly, the present invention relates to a memory apparatus of a flash memory with multi-level cells (MLCs), and an operation method thereof.
2. Description of Related Art
A flash memory is one kind of non-volatile memories, which can maintain stored data without power. The flash memories are categorized into NOR flash memories and NAND flash memories. Moreover, the flash memories can also be categorized into single level cell (SLC) flash memories and multi level cell (MLC) flash memories according to an amount of bits capable of being stored in a single memory cell. Wherein, the “single level” represents that each of the memory cells only records data of one bit, and the “multi level” represents that each of the memory cells records data of multiple bits. Since the MLC records more data bits compared to the SLC, the MLC has to distinguish values of the stored data according to more different threshold voltage distributions.
As data storage amount is increased, sensing windows between the threshold voltage distributions of the MLCs become narrower. The narrower the sensing window is, the more difficult a data state corresponding to each of the threshold voltage distributions is distinguished. FIG. 1 is a diagram illustrating threshold voltage distributions of the conventional MLCs. FIG. 2 is another diagram illustrating the threshold voltage distributions of the conventional MLCs. Referring to FIG. 1 and FIG. 2, horizontal axes of FIG. 1 and FIG. 2 represent the threshold voltages of the MLCs, and vertical axes represent numbers of the MLCs. Each of the MLCs of FIG. 1 stores 2 bits of data, so that there are four threshold voltage distributions V1-V4 are illustrated in FIG. 1, wherein the sensing window between two adjacent threshold voltage distributions is SW1. Each of the MLCs of FIG. 2 stores 4 bits of data, so that there are 16 threshold voltage distributions W1-W16 are illustrated in FIG. 2, wherein the sensing window between two adjacent threshold voltage distributions is SW2. As shown in figures, a threshold voltage difference between the threshold voltage distributions V1 and V4 is equal to a threshold voltage difference between the threshold voltage distributions W1 and W16, so that the threshold voltage distributions W1-W16 are denser than the threshold voltage distributions V1-V4, and therefore the sensing window SW2 is narrower than the sensing window SW1. Accordingly, the more bits that a single MLC stores, the narrower the sensing window between the threshold voltage distributions is. Therefore, regarding a flash memory whose a single MLC stores more bits, an occurrence chance of write operation errors or read operation errors thereof is relatively high. Therefore, how to reduce the occurrence chance of the write operation errors or the read operation errors caused by lessening of the sensing window in a MLC flash memory is a major problem to be resolved.